1. Field of the Invention
The present invention relates to a method for producing a parity check matrix for low complexity and high speed decoding, and an apparatus and method for coding a Low Density Parity Check (LDPC) code using the same; and, more particularly, to a parity check matrix producing method that can reduce complexity and decode a parity check code at high-speed by producing a parity check matrix by arraying shift values of a subblock of the parity check matrix without duplication, and producing a parity bit by classifying a linear equation on the produced parity check matrix as an independent linear equation, and an apparatus and method for coding an LDPC code using the same.
This work was supported by the IT R&D program for MIC/IITA [2006-S-002-02, “IMT-Advanced Radio Transmission Technology with Low Mobility”].
2. Description of Related Art
There are some cases that a signal transmitted in a digital format is not demodulated in a receiving part according to a state of a channel in a wired/wireless communication system. Diverse techniques are applied to the wired/wireless communication system to reduce error generation rate increasing due to high-speed communication. A channel coding technique is a representative error preventing technique which is applied to the wired/wireless communication system.
Recently, the channel coding technique is applied to most wireless communication systems. In particular, Low Density Parity Check (LDPC) codes are recognized as a next generation channel codec in the wireless communication system.
To have a look at the LDPC codes, it is assumed that the LDPC code is coded according to a systematic method. That is, a part of packet data of the LDPC code is outputted in the same format as inputted bit. A rest part of the packet data has a format that additional information corresponding to the parity bit, which is a code check bit, is consecutively added and outputted. Therefore, when the input bit is completely inputted in a block for coding, coding is performed. Also, a rate of the parity bit in the entire packet data is different according to the code rate. Also, the code rate is fixed by an H matrix, which is the parity check matrix.
The LDPC code is introduced by “Gallager”. The LDPC code is defined as a parity check matrix where the minimum number of elements has a value ‘1’ and most elements has a value ‘0’. The LDPC code is divided into a regular LDPC code and an irregular LDPC code. The regular LDPC code is an LDPC code suggested by “Gallager” where all rows in the parity check matrix have the same number of values ‘1’ as an element and all columns have the same number of values ‘1’ as an element. Differently from this, in the parity check matrix of the irregular LDPC code, there are rows including different numbers of values ‘1’ or columns including different numbers of values ‘1’. It is known that the irregular LDPC code is superior to the regular LDPC code in an error correcting function.
“Fossorier” suggests a Quasi-cyclic LDPC code showing the element of the parity check matrix as a cyclic shifted identity matrix and ‘0 matrix’, not as the elements ‘0’ and ‘1’ on matrix.
A conventional coding technology includes an efficient coding method of the LDPC suggested by “Richardson”. In this coding method, the H matrix is divided into 6 subblocks and produces an output parity bit when an input vector is given as a simultaneous equation of the matrix. The subblocks include a simple operation.
A coder of a more simple coding method suggested by Motorola Inc. is reflected on the standard report of “802.16e”. The LDPC coder suggest by Motorola Inc. is not operated using a matrix as a method suggested by “Richardson ” but directly acquires a parity bit through a simultaneous equation.
The conventional LDPC code coding technology divides the parity check matrix into blocks and produces a parity check bit through a related matrix equation. Otherwise, the conventional LDPC code coding technology calculates all input values corresponding to the parity check matrix and acquires an output of the parity check bit produced after a coding procedure through an exact matrix and simultaneous equation. The conventional LDPC code coding technology has a problem that complexity increases according to increase of the subblock size in realization as hardware and it is difficult to solve the simultaneous equation on the parity bit.
In the conventional LDPC code coding technology, when the parity check matrix is applied to an LDPC decoding technology for decoding the produced coder, complexity increases according to increase of the subblock size and a decoding speed decreases since it is not proper to a parallel process.